Split Phase-Data Synchronizer and Decoder
Waveform A is timing diagram that shows A split-phase data signal. It consist of a series of binary digits that occur at a periodic rate. Duration of each bit and the periodic bit rate is constant but the weight of each bit, 0 or 1, is random.
To detect and process the incoming signal, we need a clock that is synchronized with the data bit. This clock signal must be derived from the data signal. A phase-lock techniques can be used to recover the data and the clock. Data transition contains information about timing. This data transition can be in negative or positive direction, but it has the same meaning for timing recovery. The binary bit weight is determined by the phase of signal. A binary 0 or 1 is a positive or negative transition, respectively, during a bit interval in split-phase data signals.
The split-phase data input A is first differentiated, to mark the locations of the data transitions. Gate the CD4046B uses the differentiated signal B, which is twice the bit rate. Phase comparator II in the PLL is used due to its insensitivity to duty cycle on both the signal and comparator inputs. Clock input of FF1 will divides the VCO frequency by two. Clock input of FF1 derived from the VCO output. The differentiated signal B is tracked by The PLL during the on intervals. The PLL also remembers the last frequency present and still provides a clock output during the off intervals. Clock input of FF1 derived from the inverted VCO output. And the input of ff2 derived from inverted output of FF1. Signal D is the recovered clock signal from the split-phase data transmission. To obtain the signal D, FF2 provides the necessary phase shift in signal C. FF3 is used to recover binary information from the phase information contained in the split-phase data. To provide initial synchronization of the PLL system we use a string of alternating 0s and 1s that precede the data transmission. [Schematic diagram source: Texas Instruments Application Report]